Hi was trying to write Both structural and Test bench code for D-flip flop using JK flip flop as well as JK-Flip flop using SR flip flop.but i was getting the some errors. Please anyone could help me outthanks in advance.Here is my Coding
- structural for D2jk
Verilog Code for 2:4 Decoder - Duration: 5:52. Beginners Point Shruti Jain 6,111 views.
Test bench code for D2jk
getting errors like this
- structural code for jk2sr
Test bench code for JK2SR
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ShivaShiva
2 Answers
Well, looks like most of those errors come from not defining inputs and outputs. You need to specify this, otherwise it will give you errors. My suggestion is to pick a coding style that makes defining these more obvious, such as:
I would also recommend rewriting
with a case statement like so:
alex.forencichalex.forencich
All IO directions should be declared. Alex posted one type. Here is another type.
And in test bench file, generally speaking, input from your design must be
reg
, and output to design must be wire
(some Exceptions, like output wire
in design. etc).ID.WID.W